An electrically erasable and programmable memory (EEPROM) includes memory cells, each including a floating-gate transistor and an access MOS transistor, which are organized in a memory plane according to a matrix of n×m cells disposed in n rows (or lines) and m columns. Each memory cell is situated at the intersection of a word line and a bit line. In this structure, a set of memory cells connected to the same word line, in a row, is called a physical page of the memory. The memory plane of such a memory is a set of pages.
An example of a prior art EEPROM memory portion is shown in FIG. 1. More precisely, the memory portion includes two columns and four rows, with which four word lines WLi to WLi+3 are associated. In each of these rows, each column includes eight bit lines (respectively BL0 to BL7 and BL8 to BL15) linked to eight memory cells. In this example, these eight cells disposed at each intersection of a column and a row thus form a memory byte.
An example of a prior art memory byte is shown in FIG. 2. Each memory cell of this byte, such as the cell Ci0, includes a floating-gate transistor FGT and an access transistor AT. The latter has its gate G connected to the word line WLi, its drain D connected to a bit line BL0, and its source S connected to the drain D of the floating-gate transistor FGT. The latter has its source connected to a source line LS and its control gate G connected to a gate control line CGL0, by way of a gate control transistor CGT0. The gate of gate control transistor CGT0 is linked to the word line WLi, whose drain D is connected to the gate selection line CGL0, and whose source S is connected to a potential common to the eight control gates of the floating-gate transistors FGT. The gate selection line CGL0 extends over all the pages of the memory plane, in a manner similar to the bit lines, and links the gates of the floating-gate transistors of each cell of the same column by way of the gate control transistor CGT. A source line LS extends in a similar manner to link the sources of each cell to the same source voltage, as explained previously.
In such a memory, each cell Cij, may store a binary information item, which may be modified by a write operation. The write operating involves positively charging the floating gate of the transistor FGT. An erase operation involves negatively charging this floating gate. The operations of erasing or writing a memory cell, and more particularly the floating-gate transistor FGT of the cell, are accomplished using a tunnel effect (e.g., Fowler Nordheim effect), for example. As a result, an erased transistor FGT exhibits a greater threshold voltage than that of the programmed transistor. When a reading voltage Vread chosen between these two threshold voltage values is applied to the control gate of the transistor FGT, it remains off if it is in an erased state and on if it is in a programmed state. This makes it possible to detect its state and to associate with it a binary value representing a stored data bit.
According to one prior art approach, collective erasure of the transistors FGT is achieved by applying a voltage of 15 to 20 V to the control gate of the transistors FGT by way of the gate control transistor CGT0, while the source line is at 0 and the drain of the transistors FGT is at a floating potential. The individual programming of the transistors FGT is achieved by applying the programming voltage Vpp to the drains of the transistors FGT via the access transistors AT, while the control gates of the transistors FGT are at 0 and the source line is at a floating potential.
A plane 1 of a prior art EEPROM memory is shown in FIG. 3, which includes eight columns of eight bits and 32 rows, i.e. a total of 2048 bits. Each word line WLi (not shown in FIG. 3) of the memory plane is controlled by a voltage signal delivered by an output of a line decoder RDEC. Each column selection line CGLj receives a voltage on the basis of a column latch (not shown) in cooperation with a column decoder CDEC. Likewise, each bit line BLj is linked to a programming latch (not shown) and to a column decoder CDEC, to send thereto the signal necessary for a desired operation. Each source line LS is connected to circuitry which brings it to the ground potential during an erase or read phase, or leaves it at a floating potential during a write phase. In this example, the memory plane thus includes several pages successively disposed over the various rows. Each page, including the page Pi considered, therefore includes eight bytes, including the two bytes Oi0 and Oi1, which are disposed at the intersections of the row i with columns 0 and 1, and are each associated with a gate control line CGL0, CGL1.
In practice, a programmable memory such as the one described above is associated with a programming method which manages write commands to engender programming cycles, of which a prior step includes the definition of a start address for writing a certain data to the memory. This address includes of the definition of the write row involved, as well as the column at which the write begins. Thereafter, another prior step includes the activation of all the latches of bit lines whose bits are involved in the write to thereafter undertake the programming cycle. During the latter, all the necessary latches of the memory have been activated. Thereafter, each programming cycle first includes a cycle of erasing all the bits of the bytes involved in the write and then an actual write cycle, in which the programming potential Vpp of the memory is brought to its programming value. This ultimately allows the simultaneous and automatic programming of all the bits having to take the value “1”, such as defined by the data to be stored. Through the previously described architecture, it is therefore apparent that each bit is independently programmable by acting specifically on the bit and word lines to which it is linked.
Such a prior art non-volatile memory may exhibit certain drawbacks. In particular, a risk exists of corruption of its data in certain circumstances, that is to say a risk that some of its data is accidentally modified, or poorly recorded or read. This may result in poor operation, or indeed a crash of the system in which this memory is installed. The particular circumstances which may lead to a corruption of the data of a memory may be linked with a phase of writing to this memory, such as a power outage, a crash of the memory controller, a computer virus or miscellaneous glitches which arise when the write phase is in full swing which may lead to a failure of all or part of the write operation (this being manifested by a corruption of the data). Moreover, this phenomenon may also arise outside of any memory write phase, simply through a modification of certain data during their retention on the memory, for example through degradation of certain transistors over time, too great a storage time, etc.
One prior art approach for at least partly addressing the problem of corruption of data of a non-volatile memory includes doubling up the memory devices, e.g., using duplicate EEPROM memories and associated components in a system, to store the same information in duplicate. This approach is expensive since it requires considerable redundant hardware, as well as complex management of several memories, e.g., by dedicated software. It also lengthens the processing time.
Another prior art approach uses a non-volatile memory integrated on a semiconductor, in which each memory bit is doubled up to likewise preserve data in duplicate. In this approach, the doubling is managed within the very structure of the memory, in an integrated manner. This approach thus slightly increases the size of the integrated circuit forming the memory, but does not significantly modify the remainder of the system, thereby reducing the increase in size and in cost overhead. In this approach, each bit is associated with a twin bit, arranged in such a way that the operation of the two twin bits is correlated with their programming being carried out simultaneously by the same control components. This structure therefore makes it possible to double up the information item stored without excessively increasing the overall size of a system, by doubling up a minimum of elements. In case of failure of a memory bit over time, the data remains present on the second twin bit and may be recovered. However, this approach may exhibit a drawback that in the case of an accident during a write phase, the information item remains lost. Indeed, as the write is carried out simultaneously on the two twin bits, any failure impacts them in the same way. Such a memory then remains as vulnerable as the conventional memory described previously with reference to FIGS. 1-3 in relation to accidents in the write phase.
Thus, a need exists for an electrically programmable non-volatile memory which is less vulnerable to the risks of data corruption than the existing approaches.